The latest release of FPGA AI Suite software, version 2024.3, is packed with enhancements that elevate your development experience. This update adds new features that address the real-world challenges developers face. From boosting performance to offering new design examples and refining compiler tools, each improvement is designed to make your work more efficient and effective. Let’s dive into the key takeaways from this release.
One of the most significant advancements in FPGA AI Suite 2024.3 is the improved performance scaling with Multilane. The new ‘num_lane’ architecture enables simultaneous processing of multiple rows of a tensor, significantly enhancing computational efficiency. Instead of scaling the number of IP instances, you are scaling the number of channels that the IP processes. This results in significantly better throughput for designs that don’t require storage of a model’s weights in external memory, also known as DDR-free designs. We support up to 4 lanes to enable fast and more efficient processing. In real-world designs, we have observed performance improvements of up to 2.7x¹.
The new example designs in FPGA AI Suite 2024.3 are tailored to streamline your development process. The Agilex™ 5 FPGA E-Series hostless example design, based on Altera’s Premium Development Kit, demonstrates an efficient and compact AI solution for models that can be fully built within the FPGA fabric. In this setup, input and output AXI-Stream interfaces are stored in FPGA on-chip memory, bypassing external DDR memory. Weights and instructions are compiled directly into the FPGA bitstream, allowing inference to be performed entirely within on-chip memory. The compiler ensures data does not overflow the stream buffer into external memory and will issue errors if the filter cache or stream buffer is too small for the graph. This DDR-free design simplifies operations, reduces power consumption, and lowers system costs by eliminating the need for off-chip memory buffer management. Additionally, the Agilex 7 FPGA PCIe-attach Open FPGA Stack-based designs provide fully tested, production-quality IP that can be controlled via JTAG and System Console, offering practical, ready-to-use solutions for efficient project development.
The compiler improvements in FPGA AI Suite are designed to give you greater control and insight into your designs. The automatic generation of files necessary for the Quartus® Prime Power and Thermal Calculator simplifies power consumption estimation. Further enhancements to the Model Analyzer provide detailed reports on auxiliary modules and include more comprehensive information in graph files to help you understand which layers are running on FPGA fabric versus on the CPU. These updates ensure that you can make informed decisions about your designs, optimizing performance and efficiency.
FPGA AI Suite 2024.3 delivers several enhancements that can significantly impact your development process. By focusing on performance, providing practical design examples, and refining compiler tools, this release addresses the challenges that are often faced by developers and offers solutions that can elevate your projects. We are excited to see how you will leverage these new features and look forward to your continued feedback as we strive to make FPGA AI Suite the best tool for your needs.
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- Download FPGA AI Suite 2024.3
- Read the 2024.3 Release Notes
- Learn more about the FPGA AI Suite here!
Note 1: Results based on FPGA AI Suite 2024.3, default single lane versus multilane settings, using copies of actual customer designs.
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